Progress Update 2019/06
DLS isn't dead yet but with no scheduled release date for the next update, I thought I'd share what I'm working on.
I've implemented a switch-level simulator based on the paper "A Switch-Level Model and Simulator for MOS Digital Systems" by R. E. Bryant. You can create switch-level components which can be used inside gate-level circuits. As expected, the performance isn't great but it allows you to experiment at a lower level.
A prototype of the simulator, written in Lua, can be found at https://github.com/jdryg/lua-logic/blob/master/mossim/mossim.lua
Haven't done much testing yet so I don't know how it'll behave in complex scenarios. Currently all transistor-level circuits/components are expected to reach a steady state in finite time. I hope I'll be able to fix that and allow unstable circuits before the next update.
Logic minimization and factorization algorithms.
Started reading and experimenting with logic minimization and factorization algorithms a couple of months ago. Unfortunately I haven't managed to implement much yet. Uploaded my code on github and I hope to find some time to get back on it.
The reason I started looking into such algorithms is because while I was working on a 65C02 instruction decoder I ended up writing huge mux trees, which aren't that great with respect to propagation delay. The idea is that you can write HDL code however you want, and the minimization passes will be responsible for... minimizing the delay and component usage of the final gate network by (e.g.) convert large combinational parts into two-level networks.
And by that I mean being able to simulate an HDL component with code, instead of generating and propagating events through the gate network. Hopefully this kind of simulation should be faster than event-driven simulation currently used in DLS, but I'm not really sure yet :)
Currently working on an HDL-to-Lua converter because it's both easier to test at the moment and it will be useful for the online sandbox. Ideally I'd like to be able to translate HDL to x86_64 for the desktop versions, which should be even faster, but except from a few simple experiments with asmjit I haven't done much yet on that front.
That's all for now. Thanks for reading.
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