A downloadable game for Windows, macOS, and Linux

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Welcome to DLS, the digital logic simulator game.

The current version of the game includes:

  • Truth table levels where your goal is to build a circuit to match a given truth table, under certain restrictions (e.g. limited types of gates).
  • Sequential levels where your goal is to create a circuit to match a given timing graph.
  • Stream levels where you have to build a circuit to process several inputs streams and produce the desired outputs.
  • A powerful sandbox editor where you can build whatever circuit comes to mind! Includes a logic analyzer to debug your circuits, calculate propagation delays and/or find hazards and glitches. Create and organize components into packages and use them to create larger and better circuits.

Links

DISCLAIMER: This is an alpha version of the game. Although the simulator is capable of handling relatively complex circuits, you might find that certain configurations don't give the expected results. If this is the case, you can send us the schematic in question to find out what's going on and how we can fix the simulator.

Technical

DLS is a time-driven event-based multi-delay 3-value digital logic simulator.

  • Time-driven means that the circuit time is advanced forward based on a user-specified target speed, which is measured in circuit nanoseconds per real second (ns/s). The simulation will always advance to a new state if there are pending signals in the circuit's queue. This means that even unstable or asynchronous circuits can be correctly simulated.
  • Event-based means that a gate is simulated only if one of its inputs changes value. Otherwise the previous output is considered valid and used as input to all connected gates/components.
  • Multi-delay means that each build-in gate/component type has its own propagation delay which is always an integer greater than or equal to 1.
  • 3-value means that in addition to logic levels 0 and 1 there's an extra logic value (U for Undefined) which is used as both Z (high impedance) and X (undefined) signals, depending on its origin.

Third party libraries

DLS uses the following free software (in no particular order):

  1. GLFW - An OpenGL library (http://www.glfw.org/)
  2. bgfx - Cross-platform rendering library (https://github.com/bkaradzic/bgfx)
  3. zange - A single header ANSI C JSON parser (https://github.com/vurtun/zange)
  4. nanosvg - Simple stupid SVG parser (https://github.com/memononen/nanosvg)
  5. bnet - Message oriented networking library using TCP transport (https://github.com/bkaradzic/bnet)
  6. CrashRpt - A crash reporting system for Windows applications (http://crashrpt.sourceforge.net/)
  7. LuaJIT - a Just-In-Time Compiler for Lua (http://luajit.org/)
  8. Icons from Font Awesome - the iconic font and CSS toolkit (https://fortawesome.github.io/Font-Awesome/)
  9. Roboto font (http://www.dafont.com/roboto.font), Anonymous Pro Minus font (http://www.marksimonson.com/fonts/view/anonymous-p...)

We would like to thank their developers for building them and making them public/free.

Credits

Programming, testing: Jim Drygiannakis ( @jdryg)
Graphics/UI: Antonis Drygiannakis
Beta testing: Sam Swain, Richard Matthias, Josh Callebaut

Release history

v0.15.0 (2017-07-21)

  1. NEW: Pull up/down resistors
  2. NEW: Logic Analyzer enhancements
  3. NEW: Copy component schematic command in component's context menu
  4. NEW: Better gate/component toolbar
  5. FIX: SRAM output timings on write were wrong.
  6. FIX: Schematic file format has been changed slightly to save IO pins before everything else.

For details on previous versions, see Releases.txt or the sandbox manual.

Purchase

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5.99€ 1.97€ EUR or more

In order to download this game you must purchase it at or above the minimum price of 1.97€ EUR. You will get access to the following files:

DLS v0.15.0 (Setup x64).exe 9 MB
DLS v0.15.0 (Win x64).zip 2 MB
DLS v0.15.0 (Linux x64).zip 2 MB
DLS v0.15.0 (Mac OS X x64).zip 2 MB

Development log

Comments

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i don't understand why the \bwe pin in the SRAM component is 2 bits wide when the Din pin is more than 8 bits wide.

I just took a look at the manual and you are right, it's not clear enough.

SRAMs in DLS are word-addressable memories. If your word size is larger than 8 bits (Din width greater than 8) you have more than 1 byte per word. \bwe is an active low signal controlling which bytes of the addressed word will be written (bwe = byte write enable). 

E.g. if your word size is 16 bits and you address size is 8 bits, it means that you have 256 words or 512 bytes. But since you can only access individual words (i.e. byte pairs) you can only read or write bytes starting at even addresses. What would you do if you wanted to write only byte #5 which is the 2nd byte of the 3rd word? You should set the inputs to the following values:

  • addr = 02h
  • Din = XX12h, where XXh can be any value (SRAM should not care)
  • \bwe = 10b

This way, on the next rising edge of clk, only the 2nd byte of the 3rd word will be overwritten, leaving the 1st byte intact.

Hope it clears things up a bit. If not, I'll try a more concrete example.

i think i understand it better but the concrete example would be welcomed.

I was thinking of creating a demo circuit for you to try out the various combinations or draw some diagrams but it'll take some time. Until then please take a look at this in case it helps a bit more: https://www.ece.cmu.edu/~ece548/localcpy/sramop.pdf

If I understood correctly, what you expected to see was an 1-bit write enable input independent of the word width. Am I correct?

You are indeed correct.That's how RAM components are designed in other softwares i use, like logisim or logiccircuit.

OK. Can you perform the operation I described above in those simulators? Ie. With 16-bit words, write only 1 of the 2 word bytes on the next clock tick? 

Looking at Logisim help pages (http://www.cburch.com/logisim/docs/2.7/en/html/libs/mem/ram.html), if I understood correctly, you can only store whole words when ld=0. So in order to write only (e.g.) the 2nd byte of 16-bit word, you have to first read the word into a register, replace the 2nd byte's value and store the new 16-bit word into the SRAM. Which in turn means that you need at least 3 clock cycles.

With separate write enable signals for each word byte, as in DLS, you can do it on a single clock cycle.

is there any chance of the max bit size of a wire being 32? im trying to make a mip processor but using 2 16-bit lines instead of 32-bit is making it pretty large.

At the moment all signals are 32 bits wide internally. But I need a way to distinguish UNDEFINED and ERROR values so actual signals inside the editor are limited to 16 bits. This is because UNDEFINED/ERROR have fixed 32-bit values.

In order to make wires carry 32-bit values, signals should be either turned into a struct (32-bit value + flag for Valid/UNDEFINED/ERROR) or increase their size to 64 bits. Both of these ideas require a lot of internal changes to the simulator, which I'm currently considering but haven't managed to make yet.

So to answer your question: Not any time soon I'm afraid. Sorry about that :)

(+1)

Great game, little glichy in windowed mode. can't seem to make a input go in the top or bottom of a component (for selector lines for example)

Thanks! I'll look at the crash reports you've submitted and hopefully the bug will be fixed in the next version :)

Regarding I/O pins at the top/bottom of the component. It's in my list of things to implement at some point, but it's low priority at the moment (also, I have to figure out what to do with the name of the component in this case).

Currently I/O pins appear only one the sides of the component (left pins are always inputs and right pins are always outputs). Also, their order is the order you created them in the first place. This is also in my TODO list (being able to change the order of appearance) but I haven't decided what would be the easiest and most intuitive way to implement it (e.g. separate component symbol editor/popup or select I/O index from the port's context menu?).

(+1)

you mentioned you were thinking of a way to place the name of a component if the pins were out of top or to fix the order. i was thinking, what if you added a button in the component library next to delete where a new window would open and you can edit the apperence of the component (where default would be the current layout and the inside chip would be same, just placement of pins outside would change). in the window you could maybe move the name around relative to the chip, move pins around outside edge (with limits and therefore be able to place pin on top or change order) and maybe even move the vertex of the shape to resize, make a trapezoid for MUX, or even a V shape for a ALU. obv easier said then done but a editor window might help put pressure off you to make many different options and let them customize themselves. just an idea

That sounds great. Thanks! Don't know when I'll find some time to implement it and how far I'll take it, but it sounds interesting and it's something I'll consider.

FYI, the bug you were facing when creating a new component + package has been identified and will be fixed. Thank you again for your detailed steps to reproduce it. Apparently, I've never written the component name *before* opening the new package dialog, that's why I've missed it for so long.

In the meantime, try to create your new package before giving a name to the new component.

(+1)

Awesome. Ya a easy to miss bug, tho the glitchiness I meant earlier is when in windowed mode. everything visual seems to be shifted up one unit so it's a little hard to make connections. might be the start menu bar messing with the dimentions it thinks it's is. Also what iststs you make like like a priority value for inputs or outputs in the right click menu to change the order?

I just saw the windowed mode bug you described. Again, I've never tried running in window mode with the same dimensions as the native resolution, that's why I missed it (I usually run it in window mode, one resolution lower than the desktop resolution; i.e. my desktop is set to 1680x1050 and I run DLS in a 1600x900 window most of the time). Thanks again :)

Don't know if I'll be able to fix this because both window dimensions and cursor position come from GLFW. I'll search for a fix, but I cannot promise anything yet.

Regarding I/O priority/order. That's one of my thoughts. Don't know if I manage to implement it for the upcoming version (0.13) but it'll be done at some point.

Ok I'll do the same with resolutions. Thanks. I'll post any other bugs I find.

Hello again,

The bug related to the new component/package dialogs has been fixed in the latest version (0.13.0) I just uploaded. Unfortunately, I didn't have enough time to search for a solution to the windowed-mode issue. Hope to fix it some time soon.

Could you put on github schematics for 16-BIT FLOATING POINT ADDER from blog?

I forgot about it. 16-bit Floating point adder

I'm not sure if this is the final correct version because I have a couple of different schematics for this. If it doesn't seem to work correctly, please say it and I'll upload some of the others :)

(Edited 1 time)

How do you use the ROM? I am using the Demo version. I have seen the 7bit display but it is not clear enough.

A ROM is a combinational component (i.e. it has no clock input). Whenever addr changes the output is updated with the data at the specified address.

If you are referring to level 2.03, you have a 4-bit input and an 7-bit output (the 7-segment display; the dp input can be hardwired to a 0 constant input port). So you need 16 7-bit numbers to cover all the input numbers. Create a 7-bit by 16 words ROM, right click on it and select Edit values. At each byte (since the "words" are 7-bit long, 1 word = 1 byte) write the value it is expected by the 7-segment display to show the correct digit for the corresponding number. E.g. if the input number is 0, the ROM address would be 0, meaning the first byte. So at the first byte you should write 3F (or 0111111b where each bit is connected to a specific segment of the display). Take a look at the truth table to figure out the correct values.

Hope it clears things up a bit. If you need more details please ask again :)

(Edited 1 time)

sorry, but do you type numbers which, on the right, match the letters in the output? the 7x16 does not have enough space...

or do you take the output and type that? although I do not know what to do with the h. this seemed to me the wrong way because on the right it was just either periods or random letters.

> sorry, but do you type numbers which, on the right, match the letters in the output? the 7x16 does not have enough space...

No! You just write the the output values to each byte of the ROM. The first ROM byte should read 3F. The 2nd 06, the 3rd 5B, etc. Ignore the ASCII view (right part of the ROM editor). The ASCII view just shows the corresponding ASCII character for the byte value you have typed. But in this case this is irrelevant.

> although I do not know what to do with the h.

The 'h' next to every output value is used for showing that the value is in hexadecimal format. It's not part of the number.

I suggest you try creating some constant input ports or switches from the I/O dialog and connect them to the various inputs of the 7-segment display. Change their values and try to make the 7-segment display show the expected numbers (0, 1, 2...). Then take the bits of those inputs in turn and build 7-bit numbers. Those numbers in hexadecimal should match the expected output.

E.g. In order to show 0 on the 7-segment display, all segments should be turned on except from the middle one. Create 7 1-bit constant input ports and connect each one to A, B, C, etc. Try to make all the segments lit up except from the middle one, by manually changing each port's values. You'll get the following:

A=1, B=1, C=1, D=1, E=1, F=1, G=0.

So, the output of the ROM for address 0 (i.e. the number you want to show on the display), should be 011111 in binary, or 3F in hex.

Hope it's more clear now.

(Edited 1 time)

Thanks so much!

I'm thinking of buying the game, but Itch.io doesn't accept steam money :C

also have you though of different-bit inputs? I remember there was a level where you had to compare 2 4bit inputs with a 1bit input.

I thought I had to split the wires to add them together. for example, an and gate has 1 imput require 4 bit and the other 1 bit, so it compares the 1 bit with the other bits. as if the 1 bit wire was 4 bits of 1's or 0's.

(+1)

Thanks for very interesting app. I like to build advanced logic circuits but there is not much applications like DLS. The very old application called LogicWorks was good but it wasnt updated since many years. The other one is LogicCircuit but it is not updated also since some time. It would be great if you can add RAM module (like ROM but with W input for write and bidirectional input/output). Another thing - would it be possible to change wires in that way that if you drop end of wire onto another wire it would automaticly create T junction? For me it is a little bit strange that if I click on wire and select T junction it will start from component connection instead of this place on wire where I clicked. Another interesting feature would be visual indicator something like LED with option to select it color. Maybe it would also be possible to make bussed wires a little bit thicker? With this it would be easier to tell when looking on circuit which wires are single and which are bussed. Thanks

Thanks for your kind words and the great suggestions :)

(S)RAM component: I've been thinking about it. The only reason I haven't implemented it yet is because you can always use a scripted component to implement something similar. The problem is that there are many types of SRAMs out there (sync/async, fall-through, pipelined, burst reads/writes, etc.) and I have to study them a bit more to figure out the proper way to implement such a component. And the only reason to actually implement it is ease of use (just drop a RAM in the circuit) and the ability to inspect its contents like ROMs. Other than that, I cannot see any other benefit over scripts. I can create a simple SRAM script for you to use if you want, until I figure everything out.

Wires and T-junctions: Unfortunately, I didn't understand your suggestion. You always start a new wire from an output pin. If you drop it on an existing wire, what I would expect to happen is to connect the output pin to the input the old wire is currently connected to. No T-junction can be created in this case (each input pin has only 1 source). What you suggest might have made sense if you could start a new wire from an input pin, but that's not the case currently. Am I missing something?

Regarding how the T-junction option of the context menu works. It creates an new wire from the old wire's output pin up to the nearest node/corner. The last line segment of the new wire is from the nearest node to the mouse cursor. I could kind of fix that by rounding the right click mouse location to the nearest grid location and add an extra node there, but it won't look good with wires crossing the grid at angles other than 45/90/135/180/etc. angles. Hope it makes sense :)

LEDs: There is a LED matrix component in the toolbar. You can create a 1x1 matrix and connect an 1-bit wire to it. Please correct me if I didn't understand your suggestion. Regarding changing the color of a LED matrix, I'll add it to my TODO list.

Wire thickness: Sounds good. Will try it and see if it'll look good too :) Will report back for feedback.

Thanks again for trying out DLS. If you have anything else to share I'll be glad to hear it :)

(+1)

In case of "LED", yes, I saw that it is possible to create 1x1 LED Matrix and this is ok (anyway maybe it would be good to have directly something like single LED component) it is useful as visual indicator. But my main idea is to have option to select color - when you building big circuits you can use different colors to indicate some states of circuit. For example flags from ALU. I know also that there is output component which shows the value but visual indicator is sometimes also very useful.

As for T-junction I understand that it is some specific property because you always start from output to imput. For example creating junction is very anoying in LogicCircuit because if you want to create T-junction you need to click on wire with some keyboard button and then it splits the wire and you can connect other wire to this split point. The way which I like it is implemented in many tools like Altium Designer and LogicWorks - you can start by connecting components by any direction (you can start from output to imput but it doesnt create problems because still output is output and imput is imput, this is more editing behavior, I think). Or for example if you create mux with tri-state buffers you need to connect in some point two inputs to one output, ofcourse this works in DLS, it is just editing thing, in this other apps I could create wire from buffer to output and when I want to connect second buffer to output (with NOTed control input) I just start wire from buffer output and when I drop end of new wire to existing one it will create junction in this place.

It is described here on page 19: https://goo.gl/3pFqYY

And also on this image (the red dots are T-junctions):


As for RAM I think that it could be just simple device, I know that there are many types of memory but as always there should be some simplifications. Maybe something like this in LogicCircuit: http://www.logiccircuit.org/memory.html in this example there is separate port for data in and data out but in LogicWorks you can select if there should be input and output or bidirectional port.

If I will have other ideas I will write them here. Anyway your application is great and I thing that it is now the best logic simulator, also it is the only one with this "game" option which have great education purpose. If you will add option to add other languages I can help by translating DLS to Polish language (as I translated LogicCircuit). Greetings

PS: I created 8-bit CPU for my final thesis on my IT studies. Belowe there is partial schematic but it evolved much since this version (for example I added interrupts controller) but I was searching for app like DLS to create this new version so I think that I will soon to start building it in DLS, it would be 16-bit (I was thinking about 32-bit but I know that DLS is 16-bit max). I'm working also on FPU but I must redraw all of this in DLS because I was using LogicWorks before but it was too old and glitchy.


LED colors: Do you want to have both states (on/off) configurable (e.g. on = green, off = red) or just one color with different brightness will be enough (e.g. like it's implement now, on = light green, off = dark green)?

T-Junctions: Yes it's only an editing thing. To be honest, a couple of other users suggested that you should be able to start a wire from an input pin. It's already in my TODO list but I've categorized it as not important so it's a bit low on priority :) Hope it's not much of a hassle until it's "fixed".

RAM: As far as I can tell, the RAM described in the page you linked is async. One Write input which works as a clock signal (whenever a rising/falling edge is detected, data is written to the RAM). Problem with implementing just this version is that if you want to implement anything more sophisticated on top of it (e.g. synchronous pipelined SRAM with burst reads/writes), you'd have to build a component and you'll loose the ability to inspect the RAM's contents (once a RAM is inside a component you don't have access to it from the master schematic). That's why I'm thinking whether it'll be good to implement extra (configurable) features for it or not.

16-bit limit: Unfortunately, the way the simulator is implemented (how signals are stored and moved around and how special values such as Undefined and Error have been implemented) doesn't allow for a larger signal width at the moment. It bugs me too and it's on my list of thins to "fix", but since it's still early in development and it's supposed to be a game at some point, 16-bits should be enough for now.

Would love to see what you manage to build with DLS :)

In case of LED color I was thinking about something else - like it is implemented but with option to set LED color (green, red, blue, etc.). So before you place LED component you can select it color and then in circuit for e.g. it is dark red or green or whatever color you can pick and when on light red, green, etc. Something like standard LED.

There is a little bug - when you place buttons in a column label from other button is overlay button and it is hard to click on a button because it will open edit label dialog, maybe label should be on the left side of button?


OK about the LEDs.

Regarding the push buttons (and any other I/O port in general). This isn't actually a bug. It's by design. In order to avoid something like that, please arrange the buttons in reverse order. All ports are rendered in the same order they are created.So by reversing their order, you can hide their label behind the newer port.

Putting the label on the left side of the button will not look good in case the button has a large name. Sorry about that :)

Hi,

I'd like to inform you that several of your suggestions have been implemented and are available in the latest version (0.13.0).

  • Wire thickness based on its bit width
  • SRAM component (synchronous, flow-through, standard write)
  • Colored LEDs
and a couple of other things. If you happen to find some time to test it out, I'll be glad to hear your feedback.

Thank you very much. I will install new version and look into new features.

Sorry for delay in response, I have a lot of work. The changes are very good and useful. As far as I see they are working fine without any problems. I have some new sugestions for UI - first: could you implement more advanced save/load dialog which would allow to select directory to/from save/load?; second: component toolbar on the left. Could it be full vertical but thin? As it is now it take more place - even if components are below or above it covers more space than vertical toolbar, also on vertical toolbar there could be labels and components could be sorted by those labels for eg. logic gates, memory devices, inputs, etc. This would make component toolbar more visible clear. And third thing: maybe text component which would allow to place text note in any place in circuit. It would be useful to place descriptions of some parts/functions. I'm working on my CPU, I'm doing it in LogicWorks but soon I will start to rebuild it in DLS. LogicWorks unfortunatly refuse to cooperate with my CPU. I think that circuit is to big...

Thanks for the suggestions.

> first: could you implement more advanced save/load dialog which would allow to select directory to/from save/load?

Unfortunately, that's harder than it sounds. Implementing a proper save/load dialog using custom UI requires correct handling of Unicode paths and filenames, which in turn requires major changes to the application. This is one of those things I decided early in development and are a bit hard to change at the moment. Don't forget that even if the simulator is capable enough to handle complex circuits, my initial thought was to make some kind of game out of it. So, arbitrary save/load paths didn't fit in such scenario.

Having said that, what I have in my TODO list is the ability to add slashes as separators when saving a schematic, in order to be able to group your circuits into subfolders inside the existing schematics folder. Still needs some work to be implemented properly, but it's a lot less than what's required for what you suggest (i.e. since DLS doesn't allow non-ASCII chars in its input boxes, there's no need to handle Unicode paths).

> second: component toolbar on the left

That sounds nice. And it might be more accessible in case I add more build-in components in the future. I'll think about it.

> And third thing: maybe text component which would allow to place text note in any place in circuit.

I had that in my list, but I cannot find it anymore :) Probably removed it as not-needed. As far as I remember, what I had in mind was something like PDF comment annotations. Small symbols on the schematic grid, which you click to show/edit a comment. Is this what you have in mind? Or you want the text to be visible at all times? Maybe a "pin note" button will allow both ways to be implemented. I'll also think about it.

> LogicWorks unfortunatly refuse to cooperate with my CPU.

I haven't used LogicWorks so I'm not familiar with its capabilities. Looking at its website, it looks way more professional than DLS :)

Do you mean that it cannot simulate your schematic fast enough? Do you have any numbers which you can compare with DLS once you manage to rebuild your circuit in it? E.g. how fast is the simulation in LogicWorks (i.e. circuit nsec per wall-clock sec), like in DLS? Is there such a metric in LogicWorks?

I don't know what kind of circuits you've managed to build with DLS so far, so I'd suggest to not expect much from it performance-wise. The largest circuit I've managed to build was a cycle-accurate i8080 CPU but the simulation performance isn't great (~750usec/sec on my i3-2100).

I had that in my list, but I cannot find it anymore :) Probably removed it as not-needed. As far as I remember, what I had in mind was something like PDF comment annotations. Small symbols on the schematic grid, which you click to show/edit a comment. Is this what you have in mind? Or you want the text to be visible at all times? Maybe a "pin note" button will allow both ways to be implemented. I'll also think about it.

The double function would be good - option to pin note to always show it content or to keep only icon. Some important notes could be pinned and others which are additional could be hidden.

> LogicWorks unfortunatly refuse to cooperate with my CPU.

I haven't used LogicWorks so I'm not familiar with its capabilities. Looking at its website, it looks way more professional than DLS :)

It is not so professional as it looks, it is not updated since long time. It is interesting that it was/is very popular in students courses, almost all universities are using it

Do you mean that it cannot simulate your schematic fast enough? Do you have any numbers which you can compare with DLS once you manage to rebuild your circuit in it? E.g. how fast is the simulation in LogicWorks (i.e. circuit nsec per wall-clock sec), like in DLS? Is there such a metric in LogicWorks?

Well, it is not speed problem at this point. It is extreme laggy and it wont work at all with around half of my CPU. I think that it would be possible to somehow compare speeds. Maybe two identical circuits, CPUs, my first LogicWorks CPU (8-bit) was computing Fibonacci series.

I don't know what kind of circuits you've managed to build with DLS so far, so I'd suggest to not expect much from it performance-wise. The largest circuit I've managed to build was a cycle-accurate i8080 CPU but the simulation performance isn't great (~750usec/sec on my i3-2100).

I must check it on my i7-4790k, currently I'm using it on notebook with i5, but I have access to dual Xeon workstation, it would be funny to check performance on it ;)

PS: new idea - pull-up resistors. Sometimes when you use tri-state buffers you want 0 instead of "Z" (not connected state) https://en.wikipedia.org/wiki/Pull-up_resistor.

> I must check it on my i7-4790k, currently I'm using it on notebook with i5, but I have access to dual Xeon workstation, it would be funny to check performance on it ;)

Unfortunately, the dual Xeons won't make a difference in performance. Currently simulation is single threaded and only 8ms of frame time is devoted to it. Until I manage to move the simulation to a separate thread and it ends up being faster than the single threaded version, 8ms should be enough for smooth interaction with the schematic.

> PS: new idea - pull-up resistors. Sometimes when you use tri-state buffers you want 0 instead of "Z" (not connected state)

Aren't pull-up resistors considered analog devices (i.e. they require a Vcc or Gnd pin to work)? If yes, they don't fit into the current simulator.

Can you describe a situation where a tri-state buffer with a 0 instead of Z output would be required? The only reason there are tri-state buffers in DLS is to be able to support buses (which are effectively wire-OR structures). Is there another usage for them? Isn't it possible to use AND/OR gates in places where you need a tri-state buffer with 0 disconnected state?

(+1)

The tutorial says a bus will output the first non-undefined input, but when it has 2 defined inputs it outputs undefined.

Is this a bug? Because if not I think it should be explained better.

v0.11.1 (Linux)

You are right. I've fixed it in the manual and forgot to fix the tutorial description...

To be more specific: Originally (pre v0.10) if a bus had more than 1 non-Undefined inputs, the output returned an Error value (red wire). On v0.10 I removed all Errors from the build-in components (tri-state buffers with Undefined control pin and the bus), and I thought I should make it work like it's described in the tutorial (first non-Undefined input got forwarded to the output).

But, apparently, I never did the change, so if a bus gets more than 1 non-Undefined input, its output is Undefined.

I'll fix the description for the next release. Sorry for the confusion and thanks for reporting the bug!

PS: Actually I think a bus should behave more like an OR gate, which ignores all Undefined inputs. It should just OR together all defined inputs and return that as the result. But I think this might break some existing circuits, that's why I'm still keeping the current behavior. If you have any thoughts on the subject, I'll be glad to hear them.

Ah alright, thank you :)

(Edited 1 time) (+1)

Trying to solve "Decoding", and I connected A directly to a 3x2 Bus. I get U on output and not the A value. Why is that so?

EDIT: Hmm, I just removed the 3x2 Bus and readded it again. Now it works as expected. Maybe I hit a strange bug...

You are right. There seems to be a bug with the bus component.

Managed to reproduce it so I will most probably be able to fix it. Will upload a new version as soon as possible!

Thanks :)

Hello again,

I just uploaded a new version (0.11.1) which includes this and a couple of other bug fixes.

Thanks again for the report.

Can you do a 32bit version for windows 7?

I'll see what I can do for the next release. Problem is that it's one more build on top of 4, that's why I avoided it till now. If I do a 32-bit Win version I'll also have to do two 32-bit Linux versions :)

Could you do a build for OSX 10.10.5? I can't load the EDA simulator, as it says it requires 10.11

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Unfortunately I don't own a Mac at the moment. Somebody else is building DLS for me on OS X, so I doubt this is possible. Sorry for that. Hope you'll be able to try it out at some point in the future.

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No problem, I'll run it in a Linux VM!

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Awesome game - just got my 8 bit CPU up and running :). Would love to be able to paste into the ROM editor, I want to write a compiler for my CPU but can't deal with writing the instructions manually!

Great! Do you mind sharing your schematic? :)

You are right about the ROM editor. It should support pasting, or some other form of input (e.g. load external files). In case of pasting the problem is the format of the string/data. The problem with loading external files is that a native open file dialog won't work correctly in fullscreen mode, and writing a full file browser with the current GUI is going to be a PITA :)

Until I figure it out, you can work around the issue by using a scripted component for your ROM as I did in the 6502 schematic for the Kernal ROM (https://github.com/jdryg/dls-schematics/tree/maste...). Either extract the component from the schematic or copy/paste the script into a new component. Then, Base64 encode your ROM and paste it into the script. It should work. You can even make your compiler generate the whole script and just paste the output into DLS.

Hope that helps for now. Thanks for the feedback!

Hello again,

I'd like to inform you that in the latest version (0.9.0) I've added the ability to save and load ROM data to/from files.

In case you want to load your program into a ROM, save its byte code into a file with a ".rom" extension and place it inside the "roms" sub-folder (which is located under the current user's DLS data folder). You can then select your file via the ROM editor. Note that in case the ROM's size in bytes doesn't match the selected file size, you'll get a warning mentioning the number of bytes actually loaded.

Depending on your OS, the DLS data folder is located at:

  • Windows: %USERPROFILE%\Documents\DLS
  • Linux: The folder where you extracted the contents of the zip package.
  • OS X: ~/Documents/DLS
If the "roms" folder hasn't been created yet, you can create it manually. Otherwise, save a dummy ROM via the ROM editor, and it will be created automatically for you.
Hope it works better than pasting in the ROM editor. No need to convert your byte code to text. You can use the binary file generated by your compiler directly.

Awesome! Thank you so so much. Sorry for not sending the schematic through yet, just waiting for a free couple of hours to Polish it up. Will let you know how I get on :)

No worries :) I'm just curious to see what other people build with DLS.

The only schematics I've seen are my own and I'm a newbie on the field (still learning as I go, adding stuff to the game I think will help me build more complex circuits easily). That's why any kind of feedback is appreciated!

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./DLS
./DLS: /usr/lib/libstdc++.so.6: version `GLIBCXX_3.4.21' not found (required by ./DLS)

ls /usr/lib/libstdc++.so*
/usr/lib/libstdc++.so /usr/lib/libstdc++.so.6 /usr/lib/libstdc++.so.6.0.20

gcc --version
gcc (GCC) 4.9.3

Can you please tell me which OS (incl. version) you are using in order to try and reproduce the error? I might have to link to libstdc++ statically, but before doing that, I want to see if I can find a better solution.

Also, can you post the output of the following command:

strings /usr/lib/libstdc++.so.6 | grep GLIB

Void Linux its a rolling release so no "version"

GLIBCXX_3.4
GLIBCXX_3.4.1
GLIBCXX_3.4.2
GLIBCXX_3.4.3
GLIBCXX_3.4.4
GLIBCXX_3.4.5
GLIBCXX_3.4.6
GLIBCXX_3.4.7
GLIBCXX_3.4.8
GLIBCXX_3.4.9
GLIBCXX_3.4.10
GLIBCXX_3.4.11
GLIBCXX_3.4.12
GLIBCXX_3.4.13
GLIBCXX_3.4.14
GLIBCXX_3.4.15
GLIBCXX_3.4.16
GLIBCXX_3.4.17
GLIBCXX_3.4.18
GLIBCXX_3.4.19
GLIBCXX_3.4.20
GLIBC_2.3
GLIBC_2.2.5
GLIBC_2.14
GLIBC_2.4
GLIBC_2.18
GLIBC_2.17
GLIBC_2.3.2
GLIBCXX_DEBUG_MESSAGE_LENGTH

do let me know if I can help you with any further information....

Apparently Void seems to be stuck with GCC 4.9.3 (there's no official package for GCC 5.x). Rebuilding DLS with libstdc++ statically linked might help, but, unfortunately, I cannot comment on how long that'll take. I'll inform you once I find some time to work on it.

Sorry for the inconvenience. And thank you for your interest in DLS.

According this thread (https://forum.voidlinux.eu/t/why-is-void-still-using-gcc-4-9-3/420) you might be able to build GCC 5.2 from sources, in case you want to give it a try.

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...yeah - have you actually built gcc? on gentoo its far from a trivial sized package needing substantial build time not to mention hassle, I'd rather be patient ;)

I forgot to mention that DLS has been built with GCC 5.2.1 (objdump -s --section .comment ./DLS) so you can try to upgrade GCC, if that's an option.

I've uploaded a new package (DLS v0.8.1 (Linux x64 - GCC 4.9.3).zip) with the executable built under Void Linux x64_86 with GCC 4.9.3. Tested it in a VirtualBox VM and it seems to work.

If you happen to test, please report back any problems you might encounter.

seems to work fine, thanks for taking the time.

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amazing, well done!